1. Field of the Invention
The present invention relates to a technique of effecting simulation of a logic circuit. More particularly, it relates to an apparatus for effecting the simulation (hereinafter referred to as a logic circuit simulator) and a method for producing a semiconductor device using the logic simulation approach.
2. Description of the Related Art
A process of a logic design of a semiconductor LSI requires a step of verifying a function of a designed logic circuit, prior to a step of effecting an actual patterning of the logic circuit on a wafer. The step of verifying the function is carried out by the above logic circuit simulator.
The logic circuit simulator carries out a simulation for a logic circuit model equivalent to an actual logic circuit based on information of the logic circuit concerned (hereinafter referred to as logic circuit information) and input signal information, and outputs output signal information as a result of the simulation. The designed logic circuit concerned is estimated based on the output signal information.
The logic circuit simulator is broadly classified into two forms, i.e., the case that the simulation is carried out by software processing by means of a computer based on a simulation program and the case that the simulation is carried out by a simulator engine constituted by a dedicated hardware. In any case, logic circuit information able to be treated by the logic circuit simulator is on a level of a basic logic circuit element (gate level). As described later in detail, a technique has not been found heretofore in which a logic operation can be perfectly simulated on a transistor level subordinate to the gate level.
On the other hand, an apparatus has recently been developed which effects a simulation on a transistor level by treating a transistor as a switching element. However, this apparatus has problems in that processing speed is low and a large-scale hardware is needed.